The present invention relates to a double scan circuit, and more particularly, to a double scan circuit for inserting a new scan line obtained by interpolating adjacent interlacing scan lines into the space between lines and scanning the lines at double speed in a television.
A double scan method is generally used to maintain the resolution of an image when the screen size of a television set is increased. According to the double scan method, a television repeatedly scans the respective pixels of the screen (or the respective points on the scan line) with the same image information, so as to improve the visibility of the screen.
An example of a conventional technology for double scanning is shown in FIG. 1, showing the constitution of the technology currently used. For double scanning, the speed for a reading operation must be twice that for a writing operation. First-in-first-out (FIFO) line memories are generally used to accomplish this.
When scanning using a FIFO line memory, the reading speed must be twice the writing speed. For this, first and second FIFO line memories 102 and 103 are controlled by a write controller 101 and a read controller 105.
Write controller 101 counts the pulses of the write clock and produces a write address signal for first and second FIFO line memories 102 and 103. Read controller 105 counts the pulses of the read clock and produces a read address signal for first and second FIFO line memories 102 and 103.
In accordance with a write starting pulse and the write clock generated from write controller 101, the real line data (original line data) is input to the first FIFO line memory 102. Also, the interpolated line data is input to the second FIFO line memory 103. The data input to the first and second FIFO line memories 102 and 103 is read out in accordance with the control of read controller 105.
In other words, when reading out the data recorded in the first and the second FIFO line memories 102 and 103, control is performed by read controller 105 and is independent of the write control. Read controller 105 generates a read starting pulse according to the read clock whose frequency is double that for write control, and applies it to first and second FIFO line memories 102 and 103. Read controller 105 reads out the original data of first FIFO line memories 102 and the interpolated data of second FIFO line memories 103, in the same order as that for recording and outputs them to a multiplexer 104. Multiplexer 104 selects alternatively the outputs of first FIFO line memory 102 and second FIFO line memory 103 in accordance with the selection control signal applied to the selection control port (S) thereof and outputs the selected output as double scan data.
On the other hand, when using a double scan circuit in an image apparatus circuit, the circuit should be integrated into a single chip for easy application and cost reduction. For this, the double scan circuit should have a constitution suitable for integration, such as in the case of VLSI circuits. However, as shown in FIG. 1, in the conventional technology, the circuit for controlling FIFO line memories is complex and a large number of memory cells is required for incorporating FIFO-type line memories within a chip, which leads to a problem for VLSI implementation.
Meanwhile, U.S. Pat. No. 5,177,609 discloses an image processing system for performing a time-based compression of an image and sampling the compressed image at double speed. Also, U.S. Pat. No. 5,115,312 discloses a circuit for sequentially scanning an interpolated chrominance signal (or its luminance signal) and an original chrominance signal (or its luminance signal) at double speed, using line memories in the double scan circuit of a television.